Systolic Array Library for Hardware Genetic Algorithms

Genetic Algorithms (GAs) are commonly used search algorithms and there is an incentive in accelerate their execution speed using hardware. We present a collection of systolic array designs which perform the Selection, Crossover and Mutation operations of the GA. Although the premise there is considerable generality in the genetic operators is true, it is accepted that GAs often use di erent techniques depending on the problem being solved. We have therefore included additional arrays which can be implemented to perform alternative or complementary operations. The data ow through the arrays allows di erent arrays to be implemented independently of others in the con guration. The intention is to form a library of operators which can be used to implement a tailored GA, based on a plug and play approach. We propose a parallel processing model to this end which uses a general purpose processor, coupled with a Field Programmable Gate Array. This allows a mixed hardware/software approach to be taken to achieve acceleration.